Memory circuit with dynamic redundancy

ABSTRACT

The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of U.S. application Ser. No.09/086,625, filed May 29, 1998, entitled MEMORY CIRCUIT WITH DYNAMICREDUNDANCY, now allowed.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to memories implemented in the formof a matrix network of memory cells in an integrated circuit. Thepresent invention more specifically applies to memories provided with aredundancy element for functionally replacing a defective element of thememory (for example, a column or a row).

[0004] 2. Discussion of the Related Art

[0005] The use of a redundancy element to replace a defective elementmust be performed transparently for the user. Memory circuits are thusgenerally associated with redundancy or repair circuits, meant topermanently modify the selection of the memory columns when one of thesecolumns has failed a test. For this purpose, fuses operated during atest phase of the manufacturing process are generally used. Severalarchitectures may be used to organize the routing of the decoded columnaddresses.

[0006] A first architecture provides a redundancy column next to a groupof columns forming the matrix, and associates each column, that might bereplaced, with a fuse to connect, in the place of a defective column,the redundancy column.

[0007] A second architecture uses a fuse matrix to store the address ofthe defective column and a comparator receiving the address of thecolumn and the defective address stored by the fuse matrix. Thecomparator directs, upon each reading from or writing into the memory,the current datum to the redundancy column if the current addresscorresponds to the address stored by the fuse matrix.

[0008] More recently, redundancy circuits reducing the number ofnecessary fuses to implement replacement of a defective element of thememory have been provided. Such circuits consist of shifting, from onecolumn and from column to column, the addressing of the memory towardsthe redundancy column, each column in the memory being capable of beingused as a replacement column for the preceding column. The advantage ofsuch circuits with respect to prior solutions is that they make thetimes of access to the memory cells uniform, even in case of a use ofthe redundancy column. Examples of redundancy circuits of this type aredescribed in patents WO-A-9406082 and EP-A-0477809 which patents areincorporated herein by reference.

[0009]FIG. 1 shows a conventional example of a redundancy memory circuitof the type described in patent WO-A-9406082. This drawing shows amemory circuit including two groups or matrix networks 1, 1′ of memorycells 2, 2′ likely to each store one data bit. Each network 1, 1′includes m rows and n+1 columns, the n+1-th column forming a redundancycolumn for replacing a column containing a defective cell among the nfirst columns. Cells 2, 2′ are addressed by means of an address bus 3carrying, in the form of a binary address, the coordinates (column androw) of a memory word formed of several bits.

[0010] In the example shown, it is assumed that a memory word includestwo bits and that each network 1, 1′ is associated with one bit of amemory word. The binary address of a memory word is carried by bus 3over k bits. This address is decoded by row and column decoders 4 and 5,for extracting from address A carried by bus 3 a row address Ar and acolumn address Ac, that is, the vertical and horizontal coordinates ofthe memory word in the memory. Generally, the column address is carriedby least significant bits of address A, while the row address is carriedby most significant bits. m outputs of decoder 4 form row conductors 6enabling to select the row of the addressed memory word, a single one ofthe row conductors being active. Column decoder 5 is meant to activate acolumn conductor 7 of each group 1, 1′ corresponding to the columnaddress of the memory word.

[0011] Each matrix network 1, 1′ is associated with a data input/output8, 8′ on which the memory word is input or read. Each terminal 8, 8′ isassociated with a read amplifier 9, 9′ and with a write amplifier 10,10′. Each network 1, 1′ is further associated with a multiplexer 11, 11′for routing the data bit to a column conductor 7, 7′ of network 1, 1′.The selection of conductor 7, 7′ is performed based on column addressAc.

[0012] A redundancy circuit 12 is interposed between n outputs ofdecoder 5 and n+1 control inputs of multiplexers 11, 11′. Circuit 12 isformed by a fuse circuit 13 and a routing circuit 15. Circuits 13 and 15are, in practice, overlapping and have the function of shifting theelectric connection from an output conductor 14 of decoder 5 to aconductor 16 of next rank at the output of circuit 15 if the conductor16 of same rank as conductor 14 is associated with a column 7 or 7′including a defective cell 2 or 2′. Thus, circuit 13 includes as manyfuses as decoder 5 includes outputs 14 and circuit 15 includes as manyoutput 16 as each of networks 1 and 1′ include columns 7, 7′. If theconnection of a conductor 14 is shifted to a conductor 16 of next rank,this shifting is repeated for all conductors 14 of higher rank so thatthe conductor 14 of highest rank is associated with the redundancycolumn.

[0013] A disadvantage of conventional redundancy architectures is thatthe shifting, as concerns the addressing, of a defective column to thenext column to use the redundancy column is performed simultaneously forall networks 1, 1′ as soon as one of these networks includes a defectivecell. Thus, the circuit must include as many redundancy columns as thereare matrix networks 1, 1′ associated with a data bit even when only asingle defective column in the entire memory can be corrected orrepaired by the redundancy columns.

[0014] Another disadvantage of conventional circuits equipped withredundancy elements is that they use destructive fusible elements (forexample, which can be fused by laser or electric current) or the stateof which is modified irreversibly to modify, from the addressingviewpoint, the organization of the columns of the matrix networks. Thisleads, in practice, to implementing a redundancy element only duringtests performed during the memory manufacturing. Indeed, it is generallynot desirable to enable an end user to act in a definitive manner uponthe internal structure of an integrated circuit. Now, the failure of thememory cell may occur during the operation of a system with which thememory is associated. In such a case, the memory circuit conventionallybecomes unusable even when a redundancy element can remain available.

SUMMARY OF THE INVENTION

[0015] The present invention aims at overcoming the disadvantages ofconventional redundancy memory circuits.

[0016] The present invention more generally relates to any integratedmatrix structure of identical elements associated with at least oneredundancy element to take over the operation of a defective element.These can be, for example, identical operators implemented in the formof a matrix network in an integrated circuit in one or two directions(for example, operators organized in systolic architecture), or evenmore complex elements (for example, processors) which are either usedindividually by an adapted selection addressing in a matrix networkincluding several of these elements, or used in parallel by allreceiving common information in a first direction and one or severalindividualized pieces of information in a second direction. Except formemories, the more the integrated element is complex, the more thiselement risks to have a temporary operation failure linked, for example,to a non-reproducible malfunction during a system initializationprocedure.

[0017] According to a first aspect, the present invention aims atenabling a dynamic and reversible repair of a defect in a memory cell byusing a redundancy element.

[0018] More generally, according to this first aspect, the presentinvention aims at enabling the use of a redundancy element in anintegrated circuit including a matrix structure of identical elements byrepairing, dynamically and reversibly, a failure of one of the elementsby the use of the redundancy element.

[0019] The present invention also aims at combining a reversible repairwith an irreversible repair. According to a second aspect, the presentinvention aims at optimizing the use of redundancy lines (rows orcolumns) in a memory by inhibiting the operation of a line including adefective cell, which is different from one matrix network to the otherin a circuit including several matrix networks all simultaneouslyaddressed according to a first direction.

[0020] To achieve these and other objects, the present inventionprovides an integrated circuit including at least one matrix network ofidentical elements capable of being individually addressed at least in afirst direction and including, at least for this first direction, atleast one redundancy element, and means for reversibly inhibiting theoperation of a defective element and for maintaining the circuitoperation by using the redundancy element.

[0021] According to an embodiment of the present invention, the circuitfurther includes a means for definitively inhibiting the operation of adefective element.

[0022] According to an embodiment of the present invention, applied to acircuit including several matrix networks of identical elements to besimultaneously addressed in a second direction, this circuit includes,for each matrix network, a redundancy circuit for organizing the use ofa redundancy element associated with this matrix network independentlyfrom the other matrix networks.

[0023] The present invention also relates to a memory provided with atleast one matrix network of cells and at least one redundancy elementassociated with a first direction, and including at least one redundancycircuit for reversibly modifying the addressing in the first directionto use the redundancy element in the presence of a defective memory cellin the matrix network.

[0024] According to an embodiment of the present invention, applied to amemory including at least n+1 successive columns of cells, theredundancy circuit includes as many logic units as the matrix networkincludes columns, n first units including a selector for routing anaddress conductor associated with the corresponding column, either tothe memory cells associated with this column, or to the memory cellsassociated with the next column.

[0025] According to an embodiment of the present invention, each of then first units further includes a fuse for definitively inhibiting theoperation of a defective column.

[0026] According to an embodiment of the present invention, the memoryincludes several matrix networks and, for each network, at least oneredundancy element associated with a first direction and at least oneredundancy circuit, each redundancy circuit being individuallycontrollable.

[0027] The foregoing objects, features and advantages of the presentinvention will be discussed in detail in the following non-limitingdescription of specific embodiments in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1, previously described, is meant to show the state of theart and the problem to solve;

[0029]FIG. 2 shows a memory circuit architecture according to anembodiment of the present invention;

[0030]FIG. 3 shows an embodiment of a redundancy circuit according to afirst embodiment of the present invention; and

[0031]FIG. 4 partially shows a redundancy circuit according to a secondembodiment of the present invention.

DETAILED DESCRIPTION

[0032] The same elements have been referred to with the same referencesin the different drawings. For clarity, only those elements which arenecessary to the understanding of the present invention have been shownin the drawings and will be described hereafter.

[0033]FIG. 2 shows an example of an architecture of a redundancy memorycircuit according to an embodiment of the present invention. Aspreviously, the memory circuit is, for example, organized in matrixnetworks or groups 1, 1′, 1″ of memory cells 2, 2′, 2″, each group 1,1′, 1″ being associated with one of the bits of a memory word containingseveral bits. Each network includes, for example, m rows and n+1columns, the column of rank n+1 forming, for each network 1, 1′, 1″, aredundancy column or element.

[0034] The present invention will be described hereafter in relationwith a memory circuit provided with redundancy columns. It shouldhowever be noted that the present invention also applies to the casewhere the redundancy elements are formed by memory cell rows as well asto the case where redundancy elements are provided in both directions.

[0035] Row address Ar is, as previously, determined by a conductor inthe active state among m row conductors and is the same for all matrixnetworks 1, 1′, 1″. Column address Ac corresponds to a conductor among nconductors in an active state. Addresses Ac and Ar correspond, forexample, to the address conductors issued by decoders 4 and 5 of thecircuit shown in FIG. 1.

[0036] According to the present invention, each network 1, 1′, 1″ ofmemory cells is associated with a redundancy circuit 20, 20′, 20″ andreorganizes, independently from the possible reorganization of thecolumn addresses of the other networks, the addressing of the columnconductors in the presence of a defective memory cell.

[0037] Each group 1, 1′, 1″ also includes a circuit 21, 21′, 21″ forrouting (SEL₁₃MUX) the datum input on a terminal 8, 8′, 8″ to the columnconductor (not shown in FIG. 2) corresponding to the addressed memorycell among the n+1 columns of the group. In the embodiment shown in FIG.2, circuits 21, 21′, 21″ also integrate input/output amplifiers (I/OAMP), one input/output amplifier being associated with each columnconductor of group 1, 1′, 1″ as close as possible to the memory cells ofthis group. Indeed, recent memories are most often provided to operatewith signal levels, especially in the read mode, which are very low,which leads to placing the input/output amplifiers as close as possibleto the memory cells. Such an architecture appears in particular in thecase of a DRAM.

[0038] Each redundancy circuit receives the n column addresses Ac andincludes n+1 column conductor outputs, the n+1-th output being used incase of a failure of a cell of a column of lower rank. Preferably, thereorganization of the column addresses is performed, as in theconventional case shown in FIG. 1, by a successive shifting of thecolumn conductors from the conductor of the defective cell. Each circuit20, 20′, 20″ also includes an input 22, 22′, 22″ of reception of a shiftcontrol signal (repair) and an output 23, 23′, 23″ indicative of the useof the redundancy column.

[0039] The signals of repair and indication of the use of the redundancycolumn are issued and used by a circuit of control and detection ofdefective cells. This device can be formed of a conventional test systemor can be formed of a test circuit 24 (shown in dotted lines in FIG. 2)for automatically detecting a defective cell and then controlling theshifting of the address of the column including this defective cell tothe next column, and so on.

[0040] According to the present invention, the means used to organizethe shifting of the column conductors to the next conductors arevolatile means, that is, they are reset upon each powering-off of thememory circuit.

[0041]FIG. 3 shows a first embodiment of a redundancy circuit 20, 20′,or 20″ of FIG. 2. This circuit is formed of n units 29 associated withthe n first column conductors of the matrix network 1, 1′, or 1″ and ofa unit 29′ associated with the conductor of the redundancy column. The nunits 29 include a selector 30 for routing the address signal present ona conductor Ac0, Ac1, . . . , Ac(n−1), either to column C0, C1, . . . ,C(n−1) of same rank, or to the next column C1, . . . , C(n−1), Cn. Eachselector 30 here is formed of two switches 31, 32, which enableswitching between a current column and the next column. Each unit 29,29′ includes an element 33, for example, a NAND gate, of detection ofthe state of the preceding cell and an element 34, for example a MOStransistor, having the function of a reversible fuse of thecorresponding cell. Transistors 34 are controlled by a signal Rs formingan order of cell repair by the use of the next column and so on untilthe redundancy column is reached. Although signal Rs is applied on thegates of all transistors 34, it will be seen hereafter that the controlis only effective on the transistor of the addressed column, that is,the signal Ac of which is in the active state.

[0042] In the example shown in FIG. 3, the memory circuit is formed ofseveral sets of network 1, 1′, 1″ and the selection of a set of networksor another is performed via a predecoding address As which enablesidentification of which of the network sets is selected. Such anarchitecture is optional. In the present example, the selection means isformed, for each unit 29, of a NOR gate 35, a first input of whichreceives selection address As, and a second input of which receives theoutput of switch 31 of the current unit. Column conductor C0, C1,C(n−1), Cn corresponds to the output terminal of gate 35 and isconnected to the gate of a MOS transistor 36 connected in series betweena first terminal of a transistor 34 of the corresponding cell and theground. In the absence of a predecoding, the column conductor isconnected, via an inverter, to the output of switch 31. A secondterminal of transistor 34 is connected to a non-inverting controlterminal of switch 31, to an inverting input of switch 32 and to a firstinput of gate 33 of the corresponding unit 29. A second input of gate 33of each unit 29, 29′, except for the first one, is connected to thesecond terminal of transistor 34 of the unit of lower rank. The outputof gate 33 of each unit 29 is connected to the input of an inverter 37,the output of which is connected to the first input of gate 33. Theoutput of gate 33 of a given unit 29 is also connected to the gate of aMOS transistor 38 of the next unit 29, 29′, this transistor 38 beingconnected in series with a MOS transistor 39 between a positive supplyterminal Vdd and the output terminal of the switch 32 of the precedingcell. This output terminal of each switch 32 is also connected to thesecond input terminal of gate 35 of the next unit. The output of gate 33of each unit 29 is further connected to an inverting control terminal ofswitch 31 and to a non-inverting control terminal of the switch 32 ofthis unit.

[0043] The second input of gate 33 of the first unit 29 is connected tovoltage Vdd. It should be noted that gate 33 of the first unit 29 isoptional. It is however used in practice because it simplifies thereproduction of the redundancy circuit by enabling a repetition of unitshaving the same components. The output terminal of inverter 37 of thelast unit 29 forms terminal 23 (FIG. 2) indicative of the use of the (orof the last) redundancy column.

[0044] The testing of a memory circuit according to the presentinvention can be performed conventionally, during manufacturing, from amemory bitmap which is compared to a previously stored model. In case ofdivergences, the position of the defects enables to determine from whichcolumn conductor the shifting has to be performed.

[0045] An advantage of the present invention is that it corrects otherdefects than defects proper to networks 1, 1′, 1″ of memory cells.Indeed, these can be a defect in the input/output amplifier associatedwith the column conductor, in the routing multiplexer of the datumpresent on terminal 8, 8′, 8″ associated with the column in which thecell is identified as defective, and in any other possible componentindividually associated with each of the n+1 columns of each memory cellnetwork.

[0046] The operation of a redundancy circuit such as shown in FIG. 3 isthe following. If the identification of the defective column can beperformed conventionally, the shifting from this defective column isperformed, according to the present invention, by a column scanning.

[0047] If no error is identified, the cell of rank n+1 of circuit 20 andthe corresponding column of memory cells is not used. In this case,signal Rs is in the inactive state (for example, “0”) and, for each ofunits 29, switch 31 is in the on state while switch 32, operating inreverse fashion, is in the blocked or non-conducting state. The switch31 of each selector 30 thus connects the address conductor of the unitcorresponding to the first input of gate 35 associated with thecorresponding column conductor.

[0048] Since the gate of transistor 38 of the first cell is connected tothe ground, this first transistor 38 is always on. Transistor 39 of eachunit 29, 29′ is off as long as its gate is in the high state (“1”), thatis, transistor 39 of units 29, 29′ is off for all cells of lower rankthan a possibly defective column. The second input of gate 33 of thefirst unit always is at state “1” by being connected to voltage Vdd.

[0049] If a defective column is detected, signal Rs is placed in itsactive state, which turns on transistor 34 as well as transistor 36 ofthe addressed cell. Indeed, since the gate of transistor 36 is connectedto column conductor C0, C1, C(n−1) or Cn of the corresponding unit, thistransistor is on only when the unit containing it is addressed. Theturning-on of transistors 34 and 36 forces the output of gate 33 tostate “1”, with switch 32 turning on and switch 31 turning off. As aresult, address Ac associated with the column being addressed istransferred by switch 32 onto the second input of gate 35 of the nextcolumn. State “1” of gate 33 is transferred, by being inverted, to thefirst input of gate 33 associated with the next column. Thus, selectors30 of the next columns which are controlled from the output of thecorresponding gate 33 are all controlled to cause a shifting of thecolumn conductor to the next column conductor, from the column where theerror has appeared to the redundancy column.

[0050] Unit 29 associated with the defective column is, as for itself,disconnected from the general redundancy circuit. Indeed, oncetransistors 34 and 36 have been simultaneously turned on, they can onlybe turned back off by powering off the circuit. Signal Rs can thusreturn to state “0” for the addressing of the next column.

[0051] From a static point of view, the outputs of all gates 33 of thecolumns of lower rank than a defective column are at state “0” and theoutputs of gates 33 of the defective column are at state “1”. When thesystem is powered off, this state disappears and the column shiftingalso disappears, which enables to perform a new test procedure upon eachpowering-on of the memory circuit.

[0052] An advantage of the present invention is that it enables adynamic and reversible operation of the redundancy circuit. Thus,defects appearing during the operation of the memory circuit can beisolated, by a test procedure.

[0053] In other applications of the redundancy circuit to repetitiveelements other than memories, this advantage is particularly substantialif temporary defects are likely to appear. The redundancy column is thenused to correct a mobile defect, for example, upon each powering-on ofthe system.

[0054]FIG. 4 shows a second embodiment of a redundancy circuit accordingto the present invention. In FIG. 4, a single cell of a redundancycircuit according to this second embodiment has been shown.

[0055] A feature of this second embodiment is to associate a reversibledisconnection means (34, 36) of each column with a fuse 40 of definitivedisconnection of this column.

[0056] According to the present invention, fuse 40 is, preferably, fusedduring a memory circuit testing phase during manufacturing, to use theredundancy column in the presence of a manufacturing defect which is, bynature, permanent.

[0057] Thus, while enabling the definitive suppression of defects duringthe manufacturing of the memory circuit, the use of a free redundancycolumn, that is, of a column unused to correct a manufacturing defect,is authorized, dynamically and reversibly during the operation of thememory circuit.

[0058] The general structure of a unit 29 shown in FIG. 4 issubstantially similar to the structure discussed in relation with FIG. 3for the dynamic and reversible operation. Only the differences betweenthe two embodiments linked to the addition of a fuse 40 will bediscussed. To enable the programming of a redundancy circuit accordingto this second embodiment, the circuit includes an additional terminalRd for causing the fusing of fuse 40 of the unit 29 being addressedduring the testing to isolate the corresponding column. Inverter 37 hasbeen shown in detail in FIG. 4 and is formed of two MOS transistors 41,42, connected in series between a first terminal of fuse 40 and theground, a second terminal of fuse 40 being connected to voltage Vdd. Thegates of MOS transistors 41 and 42 are connected to the output of gate33 which forms a terminal 43′ connected to the gate of transistor 38(not shown) of the next unit. The midpoint of the series association oftransistors 41 and 42 forms the output of inverter 37 connected to thefirst input of gate 33 of the current unit. The first terminal of fuse40, which provides the biasing of inverter 37, is connected to theground via a MOS transistor 44.

[0059] If fuse 40 has not fused, that is, if the corresponding columnhas not been considered as defective during the manufacturing test, theoperation of unit 29 shown in FIG. 4 is similar to that discussed inrelation with FIG. 3. Transistor 44 is used as a fusing means for fuse40. Transistor 44 is controlled by an assembly based on MOS transistors45, 46, 47, 48, controlled by a switching to the high state of signalRd. Two transistors 47 and 48 are connected in parallel between a seriesassociation of two transistors 45 and 46 and the ground, transistor 45receiving signal Rd. The gate of transistor 45 is connected to aterminal 43, that is, to the output of gate 33 of the preceding unit.The gate of transistor 46 is connected to the output of inverter 37 ofthe current unit, and thus to a terminal 49′ corresponding to the secondinput of gate 33 of the next unit. Transistors 47 and 48 form a switchsimilar to switch 31 or 32 and illustrate an embodiment of theseswitches by analogy.

[0060] In the example shown in FIG. 4, it is assumed that a singleredundancy column is used. Thus, the fusing of a fuse 40 of a givencolumn occurs at the condition that the signal present on terminal 43 isat state “0”, that is, that no preceding column has been corrected yet.Transistor 45 to 48 are on and transistor 44 is off. It is assumed thatsignal Rd switches to state “1” to indicate a need for a definitivecolumn repair. This switching to state “1” turns on transistor 44, whichfuses fuse 40. Thus, transistor 44, turns on, which causes the fusing offuse 40. As indicated hereabove, this fusing introduces a permanent “0”on the output of inverter 37, which prevents any return to normaloperation of the corresponding column.

[0061] When fuse 40 has fused, a permanent state “0” is forced on thefirst input of gate 33 by inverter 37. Thus, selector 30 of thecorresponding unit directs address Ac via conduction means 32 and via alink 50′ to the next unit. This state “0” at the output of inverter 37also inhibits the operation of transistors 34 and 36 under the action ofa possible signal Rs. Further, this permanently forces the turning-on oftransistor 39 and, accordingly, a state “1” on the second input of gate35, and thus a state “0” on its output. Thus, transistor 36 ispermanently off, which eliminates any power consumption in the defectivememory column.

[0062] The output of gate 33 is forced to state “1”, which blocks(renders non-conducting) transistors 45 and 47 of the next unit,preventing the breakdown of another fuse.

[0063] If a single redundancy column is used per network of memorycells, a definitive repair forbids the use of a reversible repair.Conversely, if each network is associated with several redundancycolumns, there can remain available redundancy columns to perform areversible repair in addition to the definitive repair performed duringthe manufacturing of the memory circuit. The modifications to be broughtto units 29 are within the abilities of those skilled in the art basedon the desired functionality.

[0064] It should be noted that the embodiments described in relationwith FIGS. 3 and 4 may be modified according to the respective states ofrepair control signals Rs, Rd. Further, other switching means may beused provided that they respect the functional indication givenhereabove.

[0065] An advantage of the present invention is that it optimizes theuse of a memory circuit equipped with redundancy elements by enablingthe use of the redundancy elements associated with each network 1, 1′,1″ (FIG. 2) of the memory independently from one another.

[0066] Another advantage of the present invention is that it associatesa definitive repair of an element of the memory to a repair available tothe user.

[0067] Of course, the present invention is likely to have variousalterations, modifications, and improvements which will readily occur tothose skilled in the art. In particular, although the present inventionhas been described in relation with a memory circuit, the presentinvention applies, more generally, to any integrated circuit providedwith matrix networks of identical elements.

[0068] Such alterations, modifications, and improvements are intended tobe part of this disclosure, and are intended to be within the spirit andthe scope of the invention. Accordingly, the foregoing description is byway of example only and is not intended to be limiting. The invention islimited only as defined in the following claims and the equivalentthereto.

What is claimed is:
 1. An integrated circuit including at least onematrix network of identical elements capable of being individuallyaddressed at least in a first direction and including, at least for thisfirst direction, at least one redundancy element, and means forreversibly inhibiting the operation of a defective element and formaintaining the circuit operation by using the redundancy element. 2.The circuit of claim 1, further including a means for definitivelyinhibiting the operation of a defective element.
 3. The circuit of claim1, including several matrix networks of identical elements to besimultaneously addressed in a second direction, including, for eachmatrix network, a redundancy circuit for organizing the use of aredundancy element associated with this matrix network independentlyfrom the other matrix networks.
 4. A memory including at least onematrix network of cells and at least one redundancy element associatedwith a first direction, including at least one redundancy circuit ofclaim 1 for reversibly modifying the addressing in the first directionto use the redundancy element in the presence of a defective memory cellin the matrix network.
 5. The memory of claim 4, including at least n+1successive columns of cells, wherein the redundancy circuit includes asmany logic units as the matrix network includes columns, n first unitsincluding a selector for routing an address conductor associated withthe corresponding column, either to the memory cells associated withthis column, or to the memory cells associated with the next column. 6.The memory of claim 5, wherein each of the n first units furtherincludes a fuse for definitively inhibiting the operation of a defectivecolumn.
 7. The memory of claim 4, including several matrix networks and,for each network, at least one redundancy element associated with afirst direction and at least one redundancy circuit, each redundancycircuit being individually controllable.